An Accurate Gate-level Stress Estimation for NBTI

A Dynamic Timing Delay for Accurate Gate-level Circuit Simulation

A dynamic delay model, which includes the nonlinear loading effect, the effects of the input transition time and the multiple-input triggering, is proposed for the gate-level timing simulation. It is shown that the developed delay model gives near circuit-level accuracy with comparable speed to other common delay models.

Accurate NBTI-induced Gate Delay Modeling Based on Intensive SPICE Simulations

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the switching threshold voltage of pMOS transistors and as a result slows down signal propagation along the paths between flip-flops, thus it may cause functional failures in the circuit. Therefore accurate prediction of circuit aging i...

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation

Accurate logic - level power estimation

sizable errors for gates with highly loaded inputs and lightly loaded outputs [3]. The connection matrix can be used to detect conditions for which there is a transient open path between Vdd and Vss. On every input pattern transition , we check if any node that was connected to Vdd in the old input conguration is connected to Vss in the new one or viceversa. If this condition is veried, short c...

Gate-level Power Estimation Using Transition Analysis

This paper deals with the problem of estimating the power consumption of CMOS digital circuits, described at gate level. A method is proposed for computing an upper bound on the switching activity of the combinational part of a synchronous circuit. It is based on propagation of abstracted waveform sets, described down to the level of individual transitions. The view of a gate as a relation betw...